<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
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<TD ALIGN=CENTER COLSPAN='4'><B>ISE_Scanner_Project Project Status (03/09/2010 - 17:34:02)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>ISE_Scanner_Project.ise</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Placed and Routed</TD>
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<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>clock_generator</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
No Errors</TD>
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<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc3s500e-4fg320</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='F:/Tesis/FPGA\_xmsgs/*.xmsgs'>2 Warnings</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 11.1</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='F:/Tesis/FPGA\clock_generator.unroutes'>All Signals Completely Routed</A></TD>
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<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='F:/Tesis/FPGA\clock_generator.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
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<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD>Xilinx Default (unlocked)</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>0 (Setup: 0, Hold: 0)&nbsp;<A HREF_DISABLED='F:/Tesis/FPGA\clock_generator.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
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&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>9,312</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>9,312</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>3</TD>
<TD ALIGN=RIGHT>4,656</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing only related logic</TD>
<TD ALIGN=RIGHT>3</TD>
<TD ALIGN=RIGHT>3</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing unrelated logic</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>3</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT BGCOLOR='#FFFF99'><TD ALIGN=LEFT><B>Total Number of 4 input LUTs</B></TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>9,312</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='F:/Tesis/FPGA\clock_generator_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>232</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFGMUXs</TD>
<TD ALIGN=RIGHT>5</TD>
<TD ALIGN=RIGHT>24</TD>
<TD ALIGN=RIGHT>20%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCMs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>25%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>2.14</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
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&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>0 (Setup: 0, Hold: 0)</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='F:/Tesis/FPGA\clock_generator_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
<A HREF_DISABLED='F:/Tesis/FPGA\clock_generator.unroutes'>All Signals Completely Routed</A></TD>
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='F:/Tesis/FPGA\clock_generator_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>
<A HREF_DISABLED='F:/Tesis/FPGA\clock_generator.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
<TD COLSPAN='2'>&nbsp;</TD>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='F:/Tesis/FPGA\clock_generator.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>vie 2. abr 20:44:00 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='F:/Tesis/FPGA\_xmsgs/xst.xmsgs'>1 Info</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='F:/Tesis/FPGA\clock_generator.bld'>Translation Report</A></TD><TD>Current</TD><TD>vie 2. abr 20:44:24 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='F:/Tesis/FPGA\clock_generator_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>vie 2. abr 20:44:30 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='F:/Tesis/FPGA\_xmsgs/map.xmsgs'>2 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='F:/Tesis/FPGA\clock_generator.par'>Place and Route Report</A></TD><TD>Current</TD><TD>vie 2. abr 20:44:45 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='F:/Tesis/FPGA\_xmsgs/par.xmsgs'>2 Warnings</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='F:/Tesis/FPGA\_xmsgs/par.xmsgs'>4 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='F:/Tesis/FPGA\clock_generator.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>vie 2. abr 20:44:47 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='F:/Tesis/FPGA\_xmsgs/trce.xmsgs'>3 Infos</A></TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
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<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='F:/Tesis/FPGA\netgen/synthesis/clock_generator_synthesis.nlf'>Post-Synthesis Simulation Model Report</A></TD><TD>Current</TD><TD COLSPAN='2'>vie 2. abr 20:44:06 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='F:/Tesis/FPGA\netgen/translate/clock_generator_translate.nlf'>Post-Translate Simulation Model Report</A></TD><TD>Current</TD><TD COLSPAN='2'>vie 2. abr 20:59:03 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='F:/Tesis/FPGA\netgen/map/clock_generator_map.nlf'>Post-Map Simulation Model Report</A></TD><TD>Current</TD><TD COLSPAN='2'>vie 2. abr 20:57:11 2010</TD></TR>
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<br><center><b>Date Generated:</b> 04/06/2010 - 00:57:33</center>
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